The present invention relates to semiconductor devices and fabrication method thereof and more particularly to a semiconductor device having a multilayer interconnection structure and fabrication method thereof.
With progress in the art of device miniaturization, integration density of semiconductor integrated circuits is increasing year by year. On the other hand, with such increase of integration density, there arises the problem of signal delay in such a semiconductor integrated circuit caused by wiring resistance and wiring capacitance. In view of this problem of signal delay, investigations are being made these days about the technology of using low-resistance Cu for the interconnection pattern and low-dielectric organic film for the interlayer insulation film.
Because there is no known dry etching method that is effectively used for patterning Cu, it has been practiced conventionally to use a dual damascene process in the case of using Cu for the interconnection pattern, in which interconnection trenches and contact holes are formed in an interlayer insulation film in advance and the same is filled with Cu. Thus, with the dual damascene process, the contact holes and the interconnection trenches are filled with an interconnection material such as Cu, and the interconnection material is polished out from the unnecessary part by a chemical mechanical polishing (CMP) process. Thereby a planarized interconnection pattern is obtained in the form that the interconnection pattern is embedded in the contact holes and the interconnection trench. According to such a dual damascene process, there is no need of forming interconnection pattern of narrow width and large aspect ratio by an etching process, and there is no need of filling the minute spaces between the interconnection patterns by the interlayer insulation film. Thereby, it becomes possible to form highly miniaturized interconnection patterns. The effect of forming a multilayer interconnection structure with such a dual damascene process increases with increasing aspect ratio of the interconnection pattern and increasing number of interconnection layers. Thus, formation of a multilayer interconnection structure with such a dual damascene process contributes to the significant reduction of production cost of ultra-fine semiconductor devices.